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automotive data sheet rev. 2.0, 2014-05-26 BTS54220-LBA spi power controller spoc?+ 12v
BTS54220-LBA data sheet 2 rev. 2.0, 2014-05-26 revision history page or item subjects (major changes since previous revision) rev. 2.0, 2014-05-26 all general: numbering of figures and tables changed table 1 updated chapter 4.2.1 added chapter 4.2.2 added parameter p_4.1.4: number changed to p_4.1.5 and max. value improved parameter p_4.1.11: max. value improved parameter p_4.1.28: max. value improved parameter p_4.1.31: max. value improved parameter p_4.1.34: max. value improved parameter p_4.1.37: max. value improved parameter p_4.1.39: min. value improved parameter p_4.1.42: max. value improved chapter 5 rewritten (content improved) parameter p_5.3.7: max. value improved parameter p_5.3.8: test condition updated and max. value improved parameter p_5.3.10: max. value improved parameter p_5.3.13: test condition updated parameter p_5.3.14: max. value improved parameter p_5.3.16: typ. and max. value improved parameter p_5.3.17: typ. and min. value improved parameter p_5.3.23: max. value improved chapter 6.1 : r ds(on) graphs removed chapter 6.1 : r ds(on) variation factor added chapter 6.4 : description improved figure 16 : content updated chapter 6.4.4 : note added chapter 7.1 : content improved chapter 7.1 : i l(lim) graphs removed chapter 7.1 : i l(lim) variation factor added chapter 7.2 : content improved figure 18 : content updated figure 19 : content and title updated figure 20 : added undervoltage behaviour shifted from chapter 7.4 to chapter 5.2.1 figure 21 : content updated chapter 8.1 : content improved figure 22 : content updated figure 23 : content updated chapter 8.2.3 added chapter 8.4 : content improved parameter p_8.5.118 added
BTS54220-LBA data sheet 3 rev. 2.0, 2014-05-26 trademarks of infineon technologies ag aurix?, bluemoon?, c166?, ca npak?, cipos?, cipurse?, comn eon?, econopack?, coolmos?, coolset?, corecontrol?, crossave?, dave?, easypim?, econobri dge?, econodual?, econopim?, eicedriver?, eupec?, fcos?, hitfe t?, hybridpack?, i2rf?, isoface?, isopack?, mipaq?, modstack?, my-d?, novalithic?, omnitune?, optimos?, origa?, primarion?, primepack?, primestack?, pr o-sil?, profet?, rasic?, re versave?, satric?, sieget?, sindrion?, sipmos?, smarti?, smartlewis?, solid flash?, spoc?, tempfet?, thinq!?, trenchstop?, tricore?, x-go ld?, x-pmu?, xmm?, xposys?. other trademarks advance design system? (ads) of agilent te chnologies, amba?, arm?, multi-ice?, keil?, primecell?, real view?, thumb?, vision? of arm limited, uk. autosar? is licensed by autosar development partnership. bluetooth? of bluetooth sig inc. cat-iq? of dect forum. colossus?, firstgps? of trimble navigation ltd. emv? of emvc o, llc (visa holdings in c.). epcos? of epcos ag. flexgo? of microsoft corp oration. flexray? is licensed by flexray consortium. hyperterminal? of hilgraeve incorporated. iec? of commission electrot echnique internationale. irda? of infrared data parameter p_9.4.19: test condition updated parameter p_9.4.20: test condition updated parameter p_9.4.22: max. value improved parameter p_9.4.24: min. value improved parameter p_9.4.26: min. value improved parameter p_9.4.28: min. value improved parameter p_9.4.30: min. value improved parameter p_9.4.32: min. value improved parameter p_9.4.34: test condition updated and max. value improved chapter 9.5 : content improved figure 33 : content updated figure 34 : content updated chapter 9.6 : content improved chapter 9.6.3 added chapter 9.7 : content improved chapter 9.7.8 : descriptions improved and footnote added chapter 9.8 removed. redundant information figure 35 : content updated table 16 updated BTS54220-LBA parameter p_5.3.9: max. value improved parameter p_5.3.11: max. value improved parameter p_6.6.24: max. value improved parameter p_6.6.25: max. value improved table 10 split into different tables table 10 to table 12 : unit of k ilis updated parameter p_8.5.91: max. value improved parameter p_8.5.93: max. value improved parameter p_8.5.94: max. value improved rev. 1.0, 2013-03-24 all data sheet released revision history page or item subjects (major changes since previous revision)
BTS54220-LBA data sheet 4 rev. 2.0, 2014-05-26 association corporation. iso? of international organization for standardization. matlab? of mathworks, inc. maxim? of maxim integrated products, inc. microtec?, nucleus? of mentor graphics corporation. mifare? of nx p. mipi? of mipi alliance, inc. mips? of mips technologies, inc., usa. murata? of murata manufacturing co., microwave offi ce? (mwo) of applied wave research inc., omnivision? of omnivision technologies, inc. open wave? openwave systems inc. red hat? red hat, inc. rfmd? rf micro devices, inc. sirius? of sirius sate llite radio inc. solaris? of sun microsystems, inc. spansion? of spansion llc ltd. symbian? of sy mbian software limited. taiyo yuden? of taiyo yuden co. teaklite? of ceva, inc. t ektronix? of tektroni x inc. toko? of toko kabushiki kaisha ta. unix? of x/open company limited. verilog?, palladium? of cadence design systems, inc. vlynq? of texas instruments inco rporated. vxworks?, wind river? of wind river systems, inc. zetex? of diodes zetex limited. last trademarks update 2014-03-27
BTS54220-LBA table of contents data sheet 5 rev. 2.0, 2014-05-26 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 pin assignment BTS54220-LBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.1 pcb set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2.2 thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.1 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.2 stand-by mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.3 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.1.4 ready mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.5 operative mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.1.6 limp home mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2 reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.1 undervoltage on v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 output on-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 input status monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.4 power stage output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4.1 bulb and led mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4.2 switching resistive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4.3 switching inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.4.4 switching channels in parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.1 over load protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.2 over temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.3 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.4 over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.5 loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.6 loss of v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.7 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8 diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8.1 diagnosis word at spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table of contents
BTS54220-LBA table of contents data sheet 6 rev. 2.0, 2014-05-26 8.2 load current sense diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2.1 current sense signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2.2 current sense multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8.2.3 open load at on diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.3 switch bypass monitor diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.4 gate back regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 8.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9.2 daisy chain capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.5 spi protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.6 spi diagnosis registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.6.1 standard diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.6.2 errors diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.6.3 warnings diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.7 spi configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.7.1 output configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.7.2 input status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.7.3 swap configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 9.7.4 led mode configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.7.5 gate back regulation register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.7.6 hardware configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 9.7.7 diagnosis control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9.7.8 configuration register bit overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10 application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 11 package outlines BTS54220-LBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
BTS54220-LBA list of figures data sheet 7 rev. 2.0, 2014-05-26 figure 1 block diagram BTS54220-LBA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2 voltage and current definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3 pin configuration tson-24-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4 2s2p pcb cross section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5 pc board for thermal simulation with 600 mm2 cooling area. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6 pc board for thermal simulation with 2s2p cooling area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7 solder area / vias. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8 typical thermal impedance. pcb setup according figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 9 typical thermal resistance. pcb setup 1s0p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10 operation mode state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11 limp home activation as function of v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 12 v s undervoltage behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 13 r ds(on) variation factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14 input switch matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15 power stage output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16 switching a load (resistive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17 typical current limitation variation according to v ds voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 18 dynamic temperature sensor operati ons - short circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 19 dynamic and absolute temperature sensor operatio ns - overload condition . . . . . . . . . . . . . . . 40 figure 20 different counte r reset according to hwcr.rcr bit value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 21 block diagram: diagnosis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 22 current sense signal timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 23 current sense multiplexer timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 24 current sense ratio in open load at on condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 25 serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 26 combinatorial logic for ter flag. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 27 daisy chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 28 data transfer in daisy chain configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 29 timing diagram spi access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 30 relationship between si and so during spi communicati on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 31 register content sent back to c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 32 BTS54220-LBA response after an error in transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 33 BTS54220-LBA response after coming out of power-on reset at v dd . . . . . . . . . . . . . . . . . . . . . . 59 figure 34 BTS54220-LBA response in case of a negative battery voltage transi ent . . . . . . . . . . . . . . . . . . . 59 figure 35 application circuit example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 36 tson-24-3 package drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 37 tson-24 package pads and stencil. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 list of figures
BTS54220-LBA list of tables data sheet 8 rev. 2.0, 2014-05-26 table 1 product summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2 absolute maximum ra tings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 4 device capability as function of v s and v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5 device function in relation to operation modes, v s and v dd voltages . . . . . . . . . . . . . . . . . . . . . . 24 table 6 electrical characteristics power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 7 electrical characteristics power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8 electrical characteristics protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 9 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 10 electrical characteristics diagnosis k ilis 9m ? ch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 11 electrical characteristics diagnosis k ilis 27 m ? ch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 12 electrical characteristics diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 13 electrical characteristics serial pe ripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 14 spi command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 15 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 16 suggested component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 list of tables
tson-24-3 p rin BTS54220-LBA tson-24-3 BTS54220-LBA data sheet 9 rev. 2.0, 2014-05-26 BTS54220-LBA 1overview features ? 8 bit serial peripheral interface (daisy chain capable spi) for control and diagnosis ? cmos compatible parallel input pins for four channels ? selectable and- / or-combination for parallel inputs (pwm control) ? load type configuration via spi (bulbs or leds) for optimized load control ? very low stand-by current ? device ground independent from load ground ? green product (rohs-compliant) ? aec qualified description the BTS54220-LBA is a four channel high-side smart po wer switch in tson-24-3 package providing embedded protective functions. it is sp ecially designed to control standard exterior lighting in automotive applications. in order to use the same hardware, the device can be configured to bulb or led mode. as a result, both load types are optimized in terms of switching and diagnosis behavior. it is designed to drive exterior lamps up to 65 w and 27 w, hidl or the equivalent led light. configuration and status diagnosis are done via spi. an 8 b it serial peripheral interfac e (spi) is used. the spi is daisy chain capable. table 1 product summary operating voltage power switch v s 5.5 ? 28 v logic supply voltage v dd 3.8 ? 5.5 v over voltage protection v s(az,min) 42 v maximum stand-by current at 25 c i vs(stb) 1a maximum on state resistance at t j = 150 c 9 m ? channels r ds(on,max) 18.2 m ? maximum on state resistance at t j = 150 c 27 m ? channels r ds(on,max) 55 m ? spi access frequency f sclk(max) 3mhz
BTS54220-LBA overview data sheet 10 rev. 2.0, 2014-05-26 the device provides a current sense signal per channel th at is multiplexed to the diagnosis pin is. it can be enabled and disabled via spi commands. an over temper ature flag per output is pr ovided in the spi diagnosis word. a multiplexed switch bypass monitor provides short-circuit to v s diagnosis. 27 m ? channels can be configured to bul b or led mode for maximum flexibility. the BTS54220-LBA provides a fail-safe feature via a limp home input (lhi) pin and direct input pins. the power transistors are built by n-channel vert ical power mosfets with c harge pumps. the device is monolithically in tegrated in smart technology. applications ? high-side power switch for 12 v in automotive or industrial applications such as lighti ng, heating, motor driving, energy and power distribution ? especially designed for standard exterior lighting like hi gh beam, low beam, position light, tail light, brake light, parking light, license plate light, indicators and equivalent in the led technology ? replaces electromechanical relays, fuses and discrete circuits protective functions ? reverse battery protecti on with external components ? short circuit to ground protection ? stable behavior at under voltage ? current limitation ? absolute and and dynamic temperature sensor ? thermal shutdown with latch after a limited amount of retries ? overvoltage protection ? loss of ground protection ? electrostatic discha rge protection (esd) diagnostic functions ? multiplexed proportional load current sense signal (is) ? enable function for current s ense signal configurable via spi ? high accuracy of current sense signal at wide load current range ? current sense ratio ( k ilis ) configurable for leds or bulbs ? very fast diagnosis in led mode ? feedback on over temperature via spi ? short circuit to v s detection ? monitoring of i nput pins status application specific functions ? fail-safe activation via lhi pin and control via input pins ? enhanced electromagnetic compatibility (emc) for bulbs as well as leds ? led mode selection available ? spi with daisy chain capability ? switch bypass monitoring for detecting short circuit to v s
BTS54220-LBA block diagram data sheet 11 rev. 2.0, 2014-05-26 2blockdiagram figure 1 block diagram BTS54220-LBA 4 3 2 channel 1 power supply driver logic gate control & charge pump clamp for inductive load load current limitation load current sense temperature sensor esd protection gnd so sclk si cs lhi vs out4 out3 out2 out1 in2 in3 in1 is vdd in4 limp home control spi current sense multiplexer switch bypass monitor led mode control blockdiagram_4chnoed.emf
BTS54220-LBA block diagram data sheet 12 rev. 2.0, 2014-05-26 2.1 terms figure 2 shows all terms used in this data sheet, wit h associated convention for positive values. figure 2 voltage and current definition in all tables of electrical characteri stics, symbols related to channels without channel number are valid for each channel separately (e.g. v ds specification is valid for v ds1 ? v ds4 ). all spi register bits are marked as follows: addr.parameter (e.g. hwcr.stb ) with the exception of the bits in the diagnosis frames which are marked only with parameter (e.g. vsmon ). i dd v dd v so v in 2 i si i cs v s i is i s vdd so si cs is vs v si v cs v sc l k v in 1 i in 1 in1 in2 i sc l k sclk v is gnd i gnd v lhi i lhi lhi out1 i l1 out2 i l2 out3 i l3 out4 i l4 v out4 v out3 v ds4 v ds3 v out2 v out1 v ds2 v ds1 i so i in 2 v in 3 i in 3 in3 v in 4 i in 4 in4 terms_4chnoed.emf
BTS54220-LBA pin configuration data sheet 13 rev. 2.0, 2014-05-26 3 pin configuration 3.1 pin assignment BTS54220-LBA figure 3 pin configuration tson-24-3 (top view ) out2 out2 out3 24 23 22 21 20 1 2 3 4 5 6 7 8 19 18 out1 out1 out1 out1 out3 17 16 15 14 13 9 10 11 12 out4 out4 out4 out4 cs sclk si so lhi is 25 vs exposed pad (bottom ) vdd gnd in2 in1 in3 in4 pinout_220noed.emf
BTS54220-LBA pin configuration data sheet 14 rev. 2.0, 2014-05-26 3.2 pin definitions and functions pin symbol i/o function power supply pins 25 vs ? positive power supply for high-side power switch 1 gnd ? ground connection 2 vdd ? logic supply (5 v) spi & diagnosis pins 3 so o serial output of spi interface 4 si i serial input of spi interface (?high? active) 5 sclk i serial clock of spi interface (?high? active) 6 cs i chip select of spi interface (?lo w? active); integrated pull up to vdd 12 is o current sense output signal limp home input pin (integrated pull-down, le ave unused limp home input pin unconnected) 7 lhi i limp home activation signal (?high? active) parallel input pins (integrated pull -down, leave unused pins unconnected) 8 in1 i input signal of channel 1 (?high? active) 9 in2 i input signal of channel 2 (?high? active) 10 in3 i input signal of channel 3 (?high? active) 11 in4 i input signal of channel 4 (?high? active) power output pins 21, 22, 23, 24 1) 1) all outputs pins of each channel must be connected together on the pcb. all pins of an output are internally connected together. pcb traces have to be designed to withstand the maximum current which can flow. out1 o protected high-side power output of channel 1 19, 20 1) out2 o protected high-side power output of channel 2 17, 18 1) out3 o protected high-side power output of channel 3 13, 14, 15, 16 1) out4 o protected high-side power output of channel 4
BTS54220-LBA electrical characteristics data sheet 15 rev. 2.0, 2014-05-26 4 electrical characteristics 4.1 absolute maximum ratings t j = -40 to +150 c; all voltages with respect to ground typical resistive loads connected to the outputs (unless otherwise specified): 9 m ? channels: r l = 2.2 ? 27 m ? channels: r l = 6.8 ? (33 ? when lgcr.ledn = ?1?) table 2 absolute maximum ratings 1) parameter symbol values unit note / test condition number min. typ. max. supply voltage power supply voltage v s -0.3 28 v ? p_4.1.1 logic supply voltage v dd -0.3 5.5 v ? p_4.1.2 reverse polarity voltage -v s(rev) ?16v 2) t jstart = 25 c t 2min. see chapter 10 for setup p_4.1.3 supply voltage for short circuit protection (single pulse) v s(sc) 028v 3) r ecu = 20 m ? l = 0 or 5 m r cable = 16 m ? /m l cable = 1 h/m p_4.1.5 permanent short circuit number channel activations all channels n rsc1 - 100 k 3) v dd = 5 v t on = 300ms p_4.1.6 voltage at power transistor v ds ?42v? p_4.1.8 supply voltage for load dump protection v s(ld) ?42v 4) r i = 2 ? t = 400 ms p_4.1.9 current through ground pin i gnd -100 25 ma t 2min. p_4.1.10 current through vdd pin i dd -25 30 ma t 2min. p_4.1.11 power stages load current |i l | ?i l(lim) a 5) p_4.1.12 maximum energy dissipation single pulse - i l(nom) 9 m ? ch. e as ? 145 mj 6) t j(0) = 150 c i l(0) = i l(nom) = p_6.6.15 p_4.1.13 maximum energy dissipation single pulse - i l(nom) 27 m ? ch. e as ? 135 mj 6) t j(0) = 150 c i l(0) = i l(nom) = p_6.6.16 p_4.1.14
BTS54220-LBA electrical characteristics data sheet 16 rev. 2.0, 2014-05-26 diagnosis pin voltage at sense pin is v is -0.3 v s v? p_4.1.24 current through sense pin is i is -10 40 ma t 2min. p_4.1.25 input pins voltage at input pins v in -0.3 6.0 v ? p_4.1.26 current through input pins i in -0.75 0.75 ma ? p_4.1.27 current through input pins i in -2.0 10 ma t 2min. p_4.1.28 spi pins voltage at chip select pin v cs -0.3 6.0 v ? p_4.1.29 current through chip select pin i cs -0.75 0.75 ma ? p_4.1.30 current through chip select pin i cs -2.0 10 ma t 2min. p_4.1.31 voltage at serial input pin v si -0.3 6.0 v ? p_4.1.32 current through serial input pin i si -0.75 0.75 ma ? p_4.1.33 current through serial input pin i si -2.0 10 ma t 2min. p_4.1.34 voltage at serial clock pin v sclk -0.3 6.0 v ? p_4.1.35 current through serial clock pin i sclk -0.75 0.75 ma ? p_4.1.36 current through serial clock pin i sclk -2.0 10 ma t 2min. p_4.1.37 current through serial output pin so i so -0.75 0.75 ma ? p_4.1.38 current through serial output pin so i so -10 2.0 ma t 2min. p_4.1.39 limp home input pin voltage at limp home input pin v lhi -0.3 6.0 v ? p_4.1.40 current through limp home input pin i lhi -0.75 0.75 ma ? p_4.1.41 current through limp home input pin i lhi -2.0 10 ma t 2min. p_4.1.42 temperatures junction temperature t j -40 150 c ? p_4.1.45 dynamic temperatur e increase while switching ? t j ?60k? p_4.1.46 storage temperature t stg -55 150 c ? p_4.1.47 esd susceptibility esd susceptibility hbm out pins vs. vs v esd -4 4 kv 7) hbm p_4.1.48 esd susceptibility hbm all pins vs. vdd v esd -1.5 1.5 kv 7) hbm p_4.1.54 esd susceptibility hbm other pins vs. gnd incl. out pins vs. gnd v esd -2 2 kv 7) hbm p_4.1.49 table 2 absolute maximum ratings 1) (cont?d) parameter symbol values unit note / test condition number min. typ. max.
BTS54220-LBA electrical characteristics data sheet 17 rev. 2.0, 2014-05-26 notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. esd resistivity to gnd v esd -500 500 v 8) cdm p_4.1.51 esd resistivity pin 1, 12, 13, 24 (corner pins) to gnd v esd1, 12, 13, 24 -750 750 v 8) cdm p_4.1.52 1) not subject to production test, specified by design. 2) device is mounted on an fr4 2s2p board according to jedec jesd51-2,-5,-7 at natural conv ection; the product (chip and package) was simulated on a 76.4 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 m cu, 2 * 35 m cu). where applicable, a thermal via array under the package contacted the first inner copper layer. 3) eol tests according to aecq100-012. thresh old limit for short circuit failures: 100 ppm. please refer to the legal disclaimer for short-circuit capability at the end of this document. 4) r i is the internal resistance of the load dump pulse generator. 5) current limitation is a protection fe ature. protection features are not designed for continuous repetitive operation. 6) pulse shape represents inductive switch off: i d(t) = i d (0) (1 - t / t pulse ); 0 < t < t pulse 7) esd resistivity, hbm according to ansi/esda/jedec js-001-2010 8) esd susceptibility, charged device model ?cdm? eia/jesd22-c101 or esda stm5.3.1 table 2 absolute maximum ratings 1) (cont?d) parameter symbol values unit note / test condition number min. typ. max.
BTS54220-LBA electrical characteristics data sheet 18 rev. 2.0, 2014-05-26 4.2 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . 4.2.1 pcb set up figure 4 2s2p pcb cross section table 3 thermal resistance parameter symbol values unit note / test condition number min. typ. max. junction to soldering point r thjsp ?2?k/w 1) t j(0) = 105 c measured to pin 25 1) not subject to production test, specified by design. p_4.2.1 junction to ambient r thja ?21?k/w 1)2) t j(0) = 105 c 2) specified r thja values is according to jedec jesd51-2,-5,-7 at nat ural convection on fr4 2s2p board; the product (chip and package) was simulated on a 76.4 * 114.3 * 1.5 mm board with 2 inner copper layers (2 * 70 m cu, 2 * 35 m cu). where applicable, a thermal via array under the package contacted the first inner copper layer. p_4.2.2 1. 5mm 70m 35m 0.3mm zth_pcb_2s2p.emf
BTS54220-LBA electrical characteristics data sheet 19 rev. 2.0, 2014-05-26 figure 5 pc board for thermal simu lation with 600 mm2 cooling area figure 6 pc board for thermal si mulation with 2s2p cooling area
BTS54220-LBA electrical characteristics data sheet 20 rev. 2.0, 2014-05-26 figure 7 solder area / vias 4.2.2 thermal impedance figure 8 typical thermal impedance. pcb setup according figure 6 0,01 0,1 1 10 100 0,0001 0,001 0,01 0,1 1 10 100 1000 zthja[k/w] time[s] bts54220lbx 2s2p 1s0p600mm2 1s0p300mm2 1s0pfootprint
BTS54220-LBA electrical characteristics data sheet 21 rev. 2.0, 2014-05-26 figure 9 typical thermal resistance. pcb setup 1s0p 20 25 30 35 40 45 50 55 60 0 100 200 300 400 500 600 700 rthja[k/w] area[mm2] bts54220lbx 1s0p
BTS54220-LBA power supply data sheet 22 rev. 2.0, 2014-05-26 5 power supply the BTS54220-LBA is supplied by two voltage sources: ? v s (analog supply voltage) ? v dd (digital supply voltage) the v s supply line is connected to a battery feed and used for the driving circuitry of the power stages, while v dd is used for the spi logic and for driving so pin. v s and v dd supply voltages have an undervoltage detection circ uit, which prevents the acti vation of the associated function in case the measured voltage is belo w the undervoltage threshold. more in detail: ? an undervoltage on v dd supply prevents spi communication. spi registers are reset to default values. the retry counters used to protect the channels are reset th erefore the channels are in ?unlimited restart? mode. ? an undervoltage on v s supply switches off all channels, even in limp home mode. the channels are enabled again as soon as v s = v s(op) . the voltage at pin vs is also monitored. in case of a negative voltage transient resulting in v s < v smon with dcr.mux ?111 b ?, any spi command sent by the micro-controller is not accepted (see chapter 9.5 for further details). an overview of channel behavior according to different v s and v dd supply voltages is shown in table 4 (the table is valid after a successful supply voltage ramp-up). table 4 device capability as function of v s and v dd v dd v dd(po) ( v dd(po) = p_5.3.17) v dd > v dd(po) v s v smon ( v smon = p_5.3.12) channels are off channels are off spi registers reset spi registers protected spi communication not available ( f sclk = 0 mhz) spi communication available 1) ( f sclk = 3 mhz) 1) spi response depends on dcr.mux value. see chapter 9.5 for further details limp home mode not available limp home mode not available v smon < v s v s(uv) ( v s(uv) = p_5.3.2) channels are off channels are off spi registers reset spi registers available spi communication not available ( f sclk = 0 mhz) spi communication available ( f sclk = 3 mhz) limp home mode available (channels are off) limp home mode available (channels are off) v s > v s(uv) 2) 2) the undervoltage condition on v s supply must be considered. see chapter 5.2.1 for further details channels cannot be controlled by spi channels can be switched on and off spi registers reset spi registers available spi communication not available ( f sclk = 0 mhz) spi communication available ( f sclk = 3 mhz) limp home mode available limp home mode available
BTS54220-LBA power supply data sheet 23 rev. 2.0, 2014-05-26 5.1 operation modes BTS54220-LBA has the following operation modes: ? stand-by mode ? idle mode ? ready mode ? operative mode ? limp home mode the transition between operation modes is determined according to these variables: ? logic level at lhi pin ? logic level at inn pins ? dcr.mux bits state ? out.outn bits state the state diagram including the possible transitions is shown in figure 10 . the behavior of BTS54220-LBA as well as some parameters may change in dependence from the operation mode of the device. furthermore, due to the undervoltage detection circuitry which monitors v s and v dd supply voltages, some changes within the same operation mode can be seen accordingly. figure 10 operation mode state diagram there are three parameters describing the behavior of BTS54220-LBA: ? status of output channels ? status of spi registers ? status of spi communication it is necessary to set dcr.mux to a value different from 111 b to command a switch on of one or more channels. in alternative it is necessary to set the lhi to ?high? - in this case the logic state of the input pins is reflected to the outputs (if there is no undervoltage condition on v s supply). powersupply_opmodes.emf dcr.mux "111" power -up idle dcr.mux ="111"or v dd < v dd(po) or hwcr.rst = "1" out.outn = "1" or inn = "high " out.outn = "0" &inn = "low" dcr.mux "111 " dcr.mux = "111 " or ( v dd < v dd(po ) & inn = "high ") or ( hwcr.rst = "1" & inn = "high") out.outn = "1" or inn = "high " out.outn = "0" or ( v dd < v dd(po) & inn = "low") or hwcr.rst = "1" lhi = "high " lhi = "low" &inn = "high" lhi = "high " lhi = "high " lhi = "low" &inn = "low" lhi = "high " ( v dd < v d d ( p o) & inn = ? l ow?) o r ( h wc r .rs t = "1" & i nn = ?l ow?) operative ready limp home stand-by note : registers which are not mentioned are considered to be in default state
BTS54220-LBA power supply data sheet 24 rev. 2.0, 2014-05-26 table 5 shows the correlation between device operation modes, v s and v dd supply voltages, and the state of the most important functions (c hannel status, spi communication and spi registers). 5.1.1 power-up the power-up condition is entered when one of the supply voltages ( v s or v dd ) is applied to the device. both supplies are rising until they are above the undervoltage thresholds v s(op) and v dd(po) therefore the internal power- on signals are set. 5.1.2 stand-by mode when BTS54220-LBA is in stand-by mode, all outputs are off. the spi registers can be programmed if v dd > v dd(po) . the current consumption is minimum (see parameter i vs(stb) ). the circuitry that monitors v s versus the threshold v smon is disabled, allowing the programmi ng of the registers. even if one input pin is set to ?high? or if one out.outn bit is set to ?1?, all outputs stay switched off. 5.1.3 idle mode in idle mode, the internal supply circ uitry is working and the device current consumption is increased. all channels are off and a command to switch on one or more outputs (either via spi or via input pins) is accepted and executed, bringing the device into oper ative mode. spi communication is possible. table 5 device function in relation to operation modes, v s and v dd voltages operation mode function v s v smon v smon >v s v s(uv) v s > v s(uv) stand-by channels off off off spi comm. available 1) 1) if v dd > v dd(po) , otherwise not available or in reset available 1) available 1) spi registers available 1) available 1) available 1) idle channels off off off spi comm. available 1) available 1) available 1) spi registers available 1) available 1) available 1) ready channels off off off spi comm. all commands rejected 1) available 1) available 1) spi registers available 1) available 1) available 1) operative channels off off follow spi and/or input pins spi comm. all commands rejected 1) available 1) available 1) spi registers available 1) available 1) available 1) limp home channels off off follow input pins spi comm. all commands rejected 1) available (read-only) 1) available (read-only) 1) spi registers available ( err_mux only) 1) available ( err_mux only) 1) available ( err_mux only) 1)
BTS54220-LBA power supply data sheet 25 rev. 2.0, 2014-05-26 5.1.4 ready mode in ready mode, one or more outputs received a command to switch on (either via spi or via input pins). nevertheless all outputs are off because of dcr.mux bits still set to 111 b . it is necessary to change the value of those bits to bring the device into o perative mode and switch on the channels. 5.1.5 operative mode operative mode is the normal operation mode of BTS54220-LBA when no limp home condition is set and one or more outputs are switched on. device curr ent consumption is specified by parameter i gnd . an undervoltage condition on v dd supply voltage brings the device into stand-by mode (if all input pins are set to ?low?) or into ready mode (if at least one input pin is set to ?high?). 5.1.6 limp home mode BTS54220-LBA enters limp home mode when lhi pin is set to ?high?. spi registers are reset to the default value after t lhi(ac) from the rising edge at pin lhi (see figure 11 for further details). spi communication is possible but only in read-only mode (spi registers can be read but cannot be written, meaning that current sensing is not available). when v s v smon the logic state detected at pin lhi is ig nored and the device doesn?t enter limp home mode. figure 11 limp home activation as function of v s 5.2 reset condition one of the following 3 conditions resets the spi registers to the default value: ? v dd is not present or below the undervoltage threshold v dd(po) ? lhi pin is set to ?high? and v s > v smon ? a reset command ( hwcr.rst set to ?1?) is executed ? err_mux , err_countern and errn bits are not cleared by a reset command (for functional safety) in particular, all channels are switched off (if the device is not in limp home mode with one or more input pins set to ?high?). in case of lack of v dd supply the internal retry counters are disabled therefore all channels are in ?unlimited restart? mode. lhi pin lhi bit spi state t lhi(ac) t < t lhi(ac),min t lhi(ac) t < t lhi(ac),min powersupply_limphomeactive.emf norm al operation reset norm al operation v s v smon
BTS54220-LBA power supply data sheet 26 rev. 2.0, 2014-05-26 5.2.1 undervoltage on v s between v s(op) and v s(uv) the undervoltage mechanism is triggered. if the device is operative and the supply voltage drops below the undervoltage threshold v s(uv) , the logic switches off the ch annels. as soon as the supply voltage v s is above the minimum operative voltage threshold v s(op) , the channels having either the corresponding input pin set to ?high? or the out.outn bit set to ?1? are switched on again (as shown in figure 12 ). figure 12 v s undervoltage behavior powersupply_uvrvs.emf t v s( op ) v s(uv) v s( h ys ) t v out v s
BTS54220-LBA power supply data sheet 27 rev. 2.0, 2014-05-26 5.3 electrical characteristics unless otherwise specified: v s = 7 v to 18 v, v dd = 3.8 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c typical resistive loads connected to the outputs (unless otherwise specified): 9 m ? channels: r l = 2.2 ? 27 m ? channels: r l = 6.8 ? (33 ? when lgcr.ledn = ?1?) table 6 electrical characteristics power supply parameter symbol values unit note / test condition number min. typ. max. vs pin operating voltage power switch v s(op) 5.5 ? 28 1) v v ds < 0.5 v p_5.3.1 undervoltage shutdown v s(uv) ??4.5voutn = on from v ds < 1 v to i ln =0a (see figure 12 ) p_5.3.2 undervoltage shutdown hysteresis v s(hys) ?350?mv 1) p_5.3.3 stand-by current for whole device with loads i vs(stb) ?0.11 a 1) v dd = 0 v v lhi = 0 v t j = 25 c p_5.3.7 stand-by current for whole device with loads i vs(stb) ?0.12.5 a 1) v dd = 0 v v lhi = 0 v t j = 85 c p_5.3.8 stand-by current for whole device with loads i vs(stb) ?820 a v dd = 0 v v lhi = 0 v t j = 150 c p_5.3.9 idle current for whole device with loads, all channels off. i vs(idle) ?2.255ma v dd = 5 v dcr.mux = 110 b p_5.3.10 operating current for whole device i gnd ? 1118ma f sclk = 0 mhz p_5.3.11 v s threshold for limp home validation v smon 0.6 1.2 1.8 v vsmon = 1 p_5.3.12 vdd pin logic supply voltage v dd 3.8 ? 5.5 1) v f sclk = 3 mhz p_5.3.13 logic supply current normal operation i dd ?125220 a f sclk = 0 mhz v cs = v dd = 5 v dcr.mux 111 b p_5.3.14 logic stand-by current i dd(stb) ?3570 a f sclk = 0 mhz v cs = v dd = 5 v dcr.mux = 111 b p_5.3.16
BTS54220-LBA power supply data sheet 28 rev. 2.0, 2014-05-26 note: characteristics show the deviat ion of parameter at the given supply voltage and junction temperature. typical values show the typical paramet ers expected from manufacturing at v s =13.5v, v dd = 4.3 v and t j =25c power-on reset threshold voltage v dd(po) 2.3 2.75 3.8 v si = 0 v sclk = 0 v cs = 0 v so from 0 to z p_5.3.17 lhi input characteristics l-input level at pin lhi v lhi(l) -0.3 ? 1.0 v lhi = 1 (see chapter 9.6.1 ) p_5.3.18 h-input level at pin lhi v lhi(h) 2.6 ? 6.0 v ? p_5.3.19 l-input current through pin lhi i lhi(l) 32775 a v lhi = 1.0 v p_5.3.20 h-input current through pin lhi i lhi(h) 73075 a v lhi = 2.6 v p_5.3.21 timings power-on wake up time t wu(po) ?200? s 1) p_5.3.22 limp home acknowledgement time t lhi(ac) 5?30 s v dd = 5 v polling of standard diagnosis (see chapter 9.6.1 ) until lhi = stb = 1 p_5.3.23 reset command delay time t d(rst) ??100 s 1) p_5.3.25 1) not subject to production test, specified by design. table 6 electrical characteristics power supply (cont?d) parameter symbol values unit note / test condition number min. typ. max.
BTS54220-LBA power stages data sheet 29 rev. 2.0, 2014-05-26 6 power stages the high-side power stages are built by n-channel vert ical power mosfets with charge pumps. there are four channels implemented in the device. each ch annel can be switched on via spi register out or via an input pin, when available. channels 2 and 3 provide a load type configuration for bulbs or leds in register lgcr (see chapter 9.7.4 ). the load type configuration can be ch anged in on- as well as in off-state. 6.1 output on-state resistance the on-state resistance r ds(on) depends mainly on the junction temperature t j . figure 13 shows the variation of r ds(on) across the whole temperature range. th e value ?1? corresponds to the typical r ds(on) measured at t j =25c. figure 13 r ds(on) variation factor the behavior in reverse polarity mode is described in chapter 7 . 6.2 input circuit there are two ways of using the input pi ns in combination with the register out by programming bit hwcr.col in register hwcr (see chapter 9.7.6 ). ? hwcr.col = 0: a channel is switched on either by the according out.outn bit or by the input pin. ? hwcr.col = 1: a channel is switched on by the according out.outn bit only, when the input pin is ?high?. in this configuration, a pwm signal can be applied to the i nput pin and the channel is activated by the spi register out (see chapter 9.7.1 ). the default state ( hwcr.col = 0) is the or-combination of the input signal and the spi-bit. in limp home mode (lhi pin set to ?high?) the combinatoria l logic is switched to or-mode to enable a channel activation via the input pins only. figure 14 shows the complete input switch matrix. 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 -40-20 0 20406080100120140 160 r ds(on) variation factor junction temperature ( c) r ds(on) variation factor ("1" = r ds(on) typical @ 25c)
BTS54220-LBA power stages data sheet 30 rev. 2.0, 2014-05-26 the zener diode protects the input circuit against esd pu lses. the current sink to ground ensures that the input signal is low in case of an open input pin. 6.3 input status monitor the level of the input stage can be monitored via the input status monitor. the input status is indicated in the out register for the available input pin. after setting the bit swcr.swr , the readout the output register out shows the state of the input pins. the input status monitor is operational only when BTS54220-LBA is not in stand-by op eration. during stand-by operation this function is not supported. figure 14 input switch matrix powerstage_inputmatrix_4chnoed.emf in1 in2 gate driver 3 gate driver 2 gate driver 1 gate driver 4 & or out3 out2 out1 out4 & or i in 1 i in 2 col inst inst2 inst1 in3 in4 & or & or i in 2 i in 3 inst3 inst4
BTS54220-LBA power stages data sheet 31 rev. 2.0, 2014-05-26 6.4 power stage output the power stages are built to be us ed in high side configuration ( figure 15 ). the power dmos switches with a dedicated slope, which is optimized in terms of electromagnetic emission (eme). defined slew rates allow lowest eme during pwm operation at low switching losses. figure 15 power stage output 6.4.1 bulb and led mode channel 2 and channel 3 can be configured in bulb and led mode via the spi initialization registers lgcr when swcr.swr = 0. the default state is lgcr.ledn = 0. during led mode the following parameters are changed for an optimized functionality with led loads: on-state resistance r ds(on) , switching timings ( t delay(on) , t delay(off) , t on , t off ), slew rates d v /d t on and d v /d t off , load current protections i l(lim) and current sense ratio k ilis . 6.4.2 switching resistive loads when switching resistive loads the following s witching times and slew rates can be considered. figure 16 switching a load (resistive) powerstage_output.emf out gnd v out vs v ds v s v out t powerstage_switchon.emf t 90% of v s 10% of v s 70% of v s d v / d t on 30% of v s 70% of v s d v / d t off 30% of v s t delay(on) t delay(off ) in / out.outn t on t off
BTS54220-LBA power stages data sheet 32 rev. 2.0, 2014-05-26 6.4.3 switching inductive loads when switching off inductive loads wi th high-side switches, the voltage v out drops below ground potential, because the inductance intends to cont inue driving the current. to prevent the destruction of the device due to overvoltage, there is a voltage clamp mechanism implem ented which limits that negat ive output voltage to a certain level ( v ds(cl) ( chapter 6.5 )). see figure 15 for details.please refer also to chapter 7.4 . the maximum allowed load induct ance is limited. 6.4.4 switching channels in parallel in case of appearance of a short circuit with channels in parallel driving a single load, BTS54220-LBA output stages are not synchronized in the restart event. when all channels connected to the same load are in temperature limitation, the channel which has cooled down the fastest do esn't wait for the other ones to be cooled down as well to restart. thus, it is not recommended to use the device with channels in parallel. note: in case of parallel channel operation, short circuit robustness may be reduced and n rsc1 is not guaranteed any more.
BTS54220-LBA power stages data sheet 33 rev. 2.0, 2014-05-26 6.5 electrical characteristics unless otherwise specified: v s = 7 v to 18 v, v dd = 3.8 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c typical resistive loads connected to the outputs (unless otherwise specified): 9 m ? channels: r l = 2.2 ? 27 m ? channels: r l = 6.8 ? (33 ? when lgcr.ledn = ?1?) table 7 electrical characteristics power stages parameter symbol values unit note / test condition number min. typ. max. output characteristics on-state resistance 9 m ? ch. r ds(on) ?9?m ? 1) v s = 9 v to 18 v i l = 7.5 a t j = 25 c p_6.6.1 on-state resistance 9 m ? ch. r ds(on) ??18.2m ? v s = 9 v to 18 v i l = 7.5 a t j = 150 c p_6.6.2 on-state resistance 27 m ? ch. r ds(on) ?27?m ? 1) v s = 9 v to 18 v i l = 2.6 a t j = 25 c lgcr.ledn = 0 p_6.6.5 on-state resistance 27 m ? ch. r ds(on) ??55m ? v s = 9 v to 18 v i l = 2.6 a t j = 150 c lgcr.ledn = 0 p_6.6.6 on-state resistance 27 m ? ch. in led mode r ds(on) ?97?m ? 1) v s = 9 v to 18 v i l = 0.6 a t j = 25 c lgcr.ledn = 1 p_6.6.7 on-state resistance 27 m ? ch. in led mode r ds(on) ??195m ? v s = 9 v to 18 v i l = 0.6 a t j = 150 c lgcr.ledn = 1 p_6.6.8 nominal load current 9 m ? ch. (all channels active) i l(nom) ?5?a 1) t a = 85 c t j < 150 c p_6.6.15 nominal load current 27 m ? ch. (all channels active) i l(nom) ?3?a 1) t a = 85 c t j < 150 c p_6.6.16 output clamp v ds(cl) 42 47 54 v i l = 20 ma p_6.6.19
BTS54220-LBA power stages data sheet 34 rev. 2.0, 2014-05-26 output leakage current per channel t j 85c 9 m ? ch. i l(off) ? 0.02 1.4 a 2) v in = 0 v or floating out.outn = 0 t j 85c stand-by or idle mode p_6.6.20 output leakage current per channel t j 85c 27 m ? ch. i l(off) ? 0.02 0.5 a 2) v in = 0 v or floating out.outn = 0 t j 85c stand-by or idle mode p_6.6.21 output leakage current per channel t j = 150c 9 m ? ch. i l(off) ?618a v in = 0 v or floating out.outn = 0 t j = 150c stand-by or idle mode p_6.6.24 output leakage current per channel t j = 150c 27 m ? ch. i l(off) ?1.76a v in = 0 v or floating out.outn = 0 t j = 150c stand-by or idle mode p_6.6.25 input characteristics l-input level v in(l) -0.3 ? 1.0 v ? p_6.6.28 h-input level v in(h) 2.6 ? 6.0 v ? p_6.6.29 l-input current i in(l) 3 2775a v in = 1.0 v p_6.6.30 h-input current i in(h) 7 3075a v in = 2.6 v p_6.6.31 timings turn-on delay to 10% v s (logical propagation delay from input inn to output outn) 9 m ? ch. t delay(on) 30 75 140 s v s = 13.5 v t j = -40 c p_6.6.32 turn-on delay to 10% v s (logical propagation delay from input inn to output outn) 9 m ? ch. t delay(on) ?45?s 1) v s = 13.5 v t j = 25 c p_6.6.96 turn-on delay to 10% v s (logical propagation delay from input inn to output outn) 9 m ? ch. t delay(on) 15 30 55 s v s = 13.5 v t j = 150 c p_6.6.97 turn-on delay to 10% v s (logical propagation delay from input inn to output outn) 27 m ? ch. t delay(on) 10 30 70 s v s = 13.5 v lgcr.ledn = 0 p_6.6.34 table 7 electrical characteristics power stages (cont?d) parameter symbol values unit note / test condition number min. typ. max.
BTS54220-LBA power stages data sheet 35 rev. 2.0, 2014-05-26 turn-on delay to 10% v s (logical propagation delay from input inn to output outn) 27 m ? ch. in led mode t delay(on) 3 1025s v s = 13.5 v lgcr.ledn = 1 p_6.6.35 turn-off delay to 90% v s (logical propagation delay from input inn to output outn) 9 m ? ch. t delay(off) 20 50 100 s v s = 13.5 v p_6.6.39 turn-off delay to 90% v s (logical propagation delay from input inn to output outn) 27 m ? ch. t delay(off) 10 30 70 s v s = 13.5 v lgcr.ledn = 0 p_6.6.41 turn-off delay to 90% v s (logical propagation delay from input inn to output outn) 27 m ? ch. in led mode t delay(off) 3 1025s v s = 13.5 v lgcr.ledn = 1 p_6.6.42 turn-on time to 90% 9 m ? ch. t on 45 95 170 s v s = 13.5 v t j = -40 c p_6.6.46 turn-on time to 90% v s 9 m ? ch. t on ?65?s 1) v s = 13.5 v t j = 25 c p_6.6.100 turn-on time to 90% v s 9 m ? ch. t on 30 55 90 s v s = 13.5 v t j = 150 c p_6.6.101 turn-on time to 90% v s 27 m ? ch. t on 30 75 180 s v s = 13.5 v lgcr.ledn = 0 p_6.6.48 turn-on time to 90% v s 27 m ? ch. in led mode t on 10 25 55 s v s = 13.5 v lgcr.ledn = 1 p_6.6.49 turn-off time to 10% v s 9 m ? ch. t off 30 70 120 s v s = 13.5 v p_6.6.53 turn-off time to 10% v s 27 m ? ch. t off 30 85 180 s v s = 13.5 v lgcr.ledn = 0 p_6.6.55 turn-off time to 10% v s 27 m ? ch. in led mode t off 10 30 55 s v s = 13.5 v lgcr.ledn = 1 p_6.6.56 table 7 electrical characteristics power stages (cont?d) parameter symbol values unit note / test condition number min. typ. max.
BTS54220-LBA power stages data sheet 36 rev. 2.0, 2014-05-26 turn-on/off matching 9 m ? ch. t on - t off -202580s v s = 13.5 v t j = -40c p_6.6.60 turn-on/off matching 9 m ? ch. t on - t off ?-5?s 1) v s = 13.5 v t j = 25c p_6.6.61 turn-on/off matching 9 m ? ch. t on - t off -50 -20 10 s v s = 13.5 v t j = 150c p_6.6.62 turn-on/off matching 27 m ? ch. t on - t off -50 -10 30 s v s = 13.5 v lgcr.ledn = 0 p_6.6.66 turn-on/off matching 27 m ? ch. in led mode t on - t off -25 -5 15 s v s = 13.5 v lgcr.ledn = 1 p_6.6.67 turn-on slew rate 30% to 70% v s 9 m ? ch. d v / d t on 0.3 0.6 0.9 v/s v s = 13.5 v p_6.6.71 turn-on slew rate 30% to 70% v s 27 m ? ch. d v / d t on 0.1 0.25 0.5 v/s v s = 13.5 v lgcr.ledn = 0 p_6.6.73 turn-on slew rate 30% to 70% v s 27 m ? ch. in led mode d v / d t on 0.35 0.88 1.75 v/s v s = 13.5 v lgcr.ledn = 1 p_6.6.74 turn-off slew rate 70% to 30% v s 9 m ? ch. -d v /d t off 0.3 0.6 0.9 v/s v s = 13.5 v p_6.6.78 turn-off slew rate 70% to 30% v s 27 m ? ch. -d v /d t off 0.1 0.25 0.5 v/s v s = 13.5 v lgcr.ledn = 0 p_6.6.80 turn-off slew rate 70% to 30% v s 27 m ? ch. in led mode -d v /d t off 0.35 0.88 1.75 v/s v s = 13.5 v lgcr.ledn = 1 p_6.6.81 output voltage drop output voltage drop limitation at small load currents all channels v ds(nl) - 1025mv i l = 50 ma lgcr.gbrn = 1 p_6.6.93 1) not subject to production test, specified by design. 2) tested at t j = -40 c table 7 electrical characteristics power stages (cont?d) parameter symbol values unit note / test condition number min. typ. max.
BTS54220-LBA protection functions data sheet 37 rev. 2.0, 2014-05-26 7 protection functions the device provides embedded protective functions, wh ich are designed to prevent ic destruction under fault conditions described in this data sheet. fault condit ions are considered as ?out side? normal operating range. protective functions are neither designed fo r continuous nor for repetitive operation. 7.1 over load protection the load current i l is limited by the device itself in case of over load or short circuit to ground. all channels have 2 steps of current limitation which are sele cted automatically depending on the voltage v ds across the power dmos as show in figure 17 . please note that v out = v s - v ds . the current limitation threshold when v ds = 5 v is taken as reference. current limitation to the value i l(lim) is realized by increasing the resistance of the output channel, which leads to fast dmos temperature rise. figure 17 typical current limitation variation according to v ds voltage 7.2 over temperature protection each channel incorporates both an absolute t j(sc) and a dynamic ? t j(sw) temperature sensor. an increase of junction temperature t j above one of the two thresholds ( t j(sc) or t j(sw) ) switches off an overheated channel to prevent destruction. any protective switch off deactiv ates the output until the temperature has reached an acceptable value. each protective switch off event increments the error co unter by one. the number of automatic reactivations is limited by n retry . if this number of retries is reached the channel turns off and latches off. the error information related to the given channel is available on the standard diagnosis and errors diagnosis. after switching off and latching off, th e only way to switch on again, is to clear all thermal counters and errors on all channels by setting hwcr.ctc bit to 1. if the channel is active (either out.outn = 1 or inn = 1) it is turned on immediately after the spi command. for the condition n < n retry the counter of automatic reactivations is reset by every channel activation if hwcr.rcr bit is set to 1. in figure 20 the different behavior of retry counters according to hwcr.rcr bit value can be seen. 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 4 8 12 16 20 24 28 current limitation variation factor drain source voltage (v) current limitation variation ("1" = i l(lim) @ v ds = 5 v)
BTS54220-LBA protection functions data sheet 38 rev. 2.0, 2014-05-26 in limp home mode, th e thermal counters of the protecti on functions are only operative if v dd is provided in the specified range. otherwise th e counters are not active and all channels are in ?unlimited restart? mode. it is not possible to reset the counters using hwcr.ctc bit as long as the spi is in limp home mode, even if the v dd is provided. in case of the short circuit to ground, current sense ratio ( k ilis ) is deactivated as soon as v ds > v ds(sb) (switch bypass monitor threshold). usually a short circuit to ground condition tends to set v ds = v s therefore in most of the cases no current sensing diagnost ic is possible in short circuit. the error information related to the given channe l are available also on warnings diagnosis ( errn bits). refer to figure 18 and figure 19 for details.
BTS54220-LBA protection functions data sheet 39 rev. 2.0, 2014-05-26 figure 18 dynamic temperature sensor operations - short circuit protection_dynt_sc.emf in / out.outn * err reset by: hwcr.ctc = 1 t i is i l(lim) i l t j t jsw t jsw err_counter 0 1 ... n retry err internal counter 0 1 0 1 0 1 0 2 1 0 t t t t t t t js w t jsw t j(sc)
BTS54220-LBA protection functions data sheet 40 rev. 2.0, 2014-05-26 figure 19 dynamic and absolute temperature sensor operations - overload condition i l(lim ) i l t t jsw t j i is protection_dynt_overload.emf in / out.outn * err reset by: hwcr.ctc = 1 err_counter 0 1 ... n retry err internal counter 0 1 0 1 0 0 2 0 t jsw t jsw t t t t t t t j(sc )
BTS54220-LBA protection functions data sheet 41 rev. 2.0, 2014-05-26 figure 20 different counte r reset according to hwcr.rcr bit value 7.3 reverse polarity protection in reverse polarity condition, power dissipation is caus ed by the intrinsic body diode of each dmos channel as well as each esd diode of the logic pins. the reverse cu rrent through the channels has to be limited by the connected loads.the current through ground pin gnd, sens e pin is, logic power supply pin vdd, spi pins, input pins and limp home input pin has to be limited as well (please refer to the maximum ratings listed on chapter 4.1 ). note: no protection mechanism like temperature protection or current limitation is active during reverse polarity. 7.4 over voltage protection in the case of supply voltages between v s(sc)max and v s(az) the output transis tors are still opera tional and follow the input or the out register. parameters are not warranted and lif etime is reduced compared to nominal voltage supply. in addition to the output clamp for inductive loads as described in chapter 6.4.3 , there is a clamp mechanism available for over voltage protection for the logic and all channels. 7.5 loss of ground in case of complete loss of the device ground connection, but loads connected to ground, the BTS54220-LBA securely changes to or stays in off-st ate. please refer to chapter 10 where an application setup is described. 7.6 loss of v s in case of loss of v s connection in on-state, all inductances of the loads have to be demagnetized through the ground connection or through an additional path from v s to ground. for example, a suppressor diode is recommended between v s and gnd. internal counter in / out.outn protection_rcr.emf 0 1 i l i l( l im ) t 2 3 4 5 err hwcr.rcr 0 (default ) 1 0 1 1 2 0 1 0 1 0 1 0 t t t t
BTS54220-LBA protection functions data sheet 42 rev. 2.0, 2014-05-26 7.7 electrical characteristics unless otherwise specified: v s = 7 v to 18 v, v dd = 3.8 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v, t j = 25 c typical resistive loads connected to the outputs (unless otherwise specified): 9 m ? channels: r l = 2.2 ? 27 m ? channels: r l = 6.8 ? (33 ? when lgcr.ledn = ?1?) table 8 electrical characteristics protection functions parameter symbol values unit note / test condition number min. typ. max. over load protection load current limitation 9 m ? ch. i l(lim) 63 82 99 a 1) v ds = 5 v p_7.7.1 load current limitation 9 m ? ch. i l(lim) ?41?a 1) v ds = 26 v p_7.7.2 load current limitation 27 m ? ch. i l(lim) 30 42 56 a 1) v ds = 5 v lgcr.ledn = 0 p_7.7.5 load current limitation 27 m ? ch. i l(lim) ?21?a 1) v ds = 26 v lgcr.ledn = 0 p_7.7.6 load current limitation 27 m ? ch. in led mode i l(lim) 9.51217a v ds = 5 v t j = -40 c lgcr.ledn = 1 p_7.7.7 load current limitation 27 m ? ch. in led mode i l(lim) ?5?a 1) v ds = 26 v lgcr.ledn = 1 p_7.7.8 over temperature protection thermal shut down temperature t j(sc) 150 170 200 c 1) p_7.7.14 thermal hysteresis of thermal shutdown ? t j(sc) ?20?k 1) p_7.7.15 dynamic temperature increase limitation while switching ? t j(sw) ?80?k 1) p_7.7.16 number of automatic retries at dynamic temperature sensor or over temperature shut down n retry ?89 1) p_7.7.17 reverse polarity drain source diode voltage during reverse polarity 9 m ? ch. v ds(rev) 400 600 740 mv i l = i l(nom) = p_6.6.15 t j = 150 c p_7.7.18
BTS54220-LBA protection functions data sheet 43 rev. 2.0, 2014-05-26 drain source diode voltage during reverse polarity 27 m ? ch. v ds(rev) 400 650 800 mv i l = i l(nom) = p_6.6.16 t j = 150 c p_7.7.19 over voltage overvoltage protection v s(az) 42 47 54 v i s = 4 ma p_7.7.22 1) not subject to production test, specified by design. table 8 electrical characteristics protection functions (cont?d) parameter symbol values unit note / test condition number min. typ. max.
BTS54220-LBA diagnosis data sheet 44 rev. 2.0, 2014-05-26 8 diagnosis for diagnosis purpose, the BTS54220-LBA provides a curren t sense signal at pin is and a diagnosis word via spi. there is a current sense multiplexer implemented that is controlled via spi. the sense si gnal can also be disabled by spi command. a switch bypass monito r allows to detect a short circuit be tween the output pin and the battery voltage. please refer to figure 21 for details. figure 21 block diagram: diagnosis for diagnosis feedback at differen t operation modes, please see table 9 . channel 1 load current sense r is i is 0 current sense multiplexer t gate control load current limitation latch temperature sensor err1 or latch dcr.mux out4 out3 out2 out1 vs is v s v ds(sb) sbm dcr. diagnosis_4ch.emf
BTS54220-LBA diagnosis data sheet 45 rev. 2.0, 2014-05-26 8.1 diagnosis word at spi diagnostic information about the status of each channel is provided through spi. in the standard diagnosis the err_mux bit reports if there is a channel which had alr eady enough restarts to reach the maximum allowed number of retries n retry (p_7.7.17). if 2 or more channels are latched off due to that, err_mux bits aren't enough to identify which channels are off. in such cases, it is possible to get an overview channel by channel using err_countern bits in errors diagnosis (see chapter 9.6.2 ) it is possible to check if one or more channels had some retries during switching on, although the limit of n retry was not reached. an overview chann el by channel of thermal coun ter status is available using errn bits in warnings diagnosis (see chapter 9.6.3 ). for both err_countern and errn the information on channel n is given at bit n-1 (e.g. bit 0 indicates status of channel 1). table 9 operation modes 1) 1) l = ?low? level, h = ?high? level, z = high impedance, pote ntial depends on leakage currents and external circuit. x = undefined. operation mode input level out.outn output level v out current sense i is error flag err_countern 2) 2) the over temperature flag is set la tched and can be cleared by setting hwcr.ctc bit to 1. warning flag errn 3) 3) the warning flags are latched until they are reset (see hwcr.rcr description). dcr.sbm bit normal operation ( channel off )l / 0 (off-state) gnd z 0 0 1 short circuit to gnd gnd z 0 0 1 thermal shut down z z 0 2) 0 2) x short circuit to v s v s z0 0 0 open load z z 0 0 x normal operation ( channel on )h / 1 (on-state) ~ v s i l / k ilis 000 current limitation < v s z0 0 x dynamic or absolute thermal limitation channel switched off zz 0 1 x dynamic or absolute thermal limitation n retry reached channel latched off zz 1 2) 1x short circuit to gnd ~gnd z 0 0 1 short circuit to v s v s < i l / k ilis 000 open load v s z0 0 0
BTS54220-LBA diagnosis data sheet 46 rev. 2.0, 2014-05-26 8.2 load current sense diagnosis there is a current sense signal available at pin is which provides a current proportional to the load current of one selected channel. the selection is done by a multiplexer which is configured via spi. 8.2.1 current sense signal the current sense signal (ratio k ilis = i l / i s ) is provided during on-state as long as no failure mode occurs. for dedicated channels the ratio k ilis can be adjusted to the load type (led or bulb) via spi register lgcr . the accuracy of the ratio k ilis depends on the load current and temperature. usually a resistor r is is connected to the current sense pin. it is recommended to use resistors 1.5 k ? < r is <5k ? . a typical value is 2.7 k ? . the current sense signal of a channel is not active when the channel is off or when the protection functions (current limitation, over temperature or dynamic temperature sensor s) are active. if the maximum number of automatic reactivations n retry is reached ( n = n retry ), the current sense signal of th e affected channel is deactivated until the reset of the counters by setting hwcr.ctc bit to 1. details about timings between the current sense signal i is and the output voltage v out and the load current i l can be found in figure 22 . figure 22 current sense signal timings 8.2.2 current sense multiplexer there is a current sense multiplexer implemented in th e BTS54220-LBA that routes the sense current of the selected channel to the diagnosis pin is. the channel is selected via spi register dcr.mux . the sense current can also be disabled by spi register dcr.mux . for details on timing of the current sense multiplexer, please refer to figure 23 . diagnosis_sensetiming.emf v out i is t t t i l t on t on t sis(on) t sis(lc) off t off t dis (off) off in / out.outn
BTS54220-LBA diagnosis data sheet 47 rev. 2.0, 2014-05-26 figure 23 current sense multiplexer timings 8.2.3 open load at on diagnosis if a channel is on in open load condition, a small curr ent can still flow, for exampl e because of humidity. the parameter i l(ol) gives the threshold of recognition for such leaka ge current. if the voltage measured at the sense resistor r sense corresponds to a current i is(ol) (4 a), then the curr ent flowing at the output in on state is within the limits given by i l(ol) . figure 24 shows the sense current behavior once a channel in open load at on condition is selected with the sense cu rrent multiplexer. the red curve show a typical product curve. the blue line shows the ideal k ilis ratio. figure 24 current sense ratio in open load at on condition 8.3 switch bypass monitor diagnosis to detect short circuit to v s , there is a switch bypass monitor implemen ted. in case of short circuit between the output pin out and vs in on-state, the current flows th rough the power transistor as well as through the short circuit (bypass) with undefined share between the two. as a result, the current sense signal shows lower values than expected by the load current. in off-st ate, the output voltage remains close to v s potential which leads to a small v ds . the switch bypass monitor compares the threshold v ds(sb) with the voltage v ds across the power transistor of that channel which is selected by the current sense multiplexer ( dcr.mux ). the result of the comparison can be read in spi register dcr.sbm . diagnosis_muxtiming.emf cs i is t 000 dcr.mux 001 110 110 t sis(en) t s is( mu x) t dis(mux) t i is i l i is(ol ) i l(ol ) i is(en)
BTS54220-LBA diagnosis data sheet 48 rev. 2.0, 2014-05-26 8.4 gate back regulation to increase the current sense accuracy, the gate back re gulation (gbr) function is implemented. this function monitors the v ds voltage at the output and if the value is equal to or lower than v ds(nl) the output dmos gate is partially discharged. this increases output dmos resistance so that v ds = v ds(nl) even for very small output currents. the v ds increase allows the cu rrent sensing circuitry to work with better accuracy, providing tighter k ilis values for output curr ents in the low range. this function is active by default ( lgcr.gbrn bits set to ?1? after a reset). according to output current, gbr function can be left active or disabl ed. even if left active, gate back regulation circuitry may not be working because the measured v ds is bigger than v ds(nl) (depending on output current, junction temperature, output dmos resistance). due to production and temperature vari ations, gbr circuitry can affect ki lis performance in negative way for some output current values. for this reason, table 10 and table 11 indicate for which output currents it is necessary to deactivate gbr (setting the corresponding lgcr.gbrn bit to ?0?) to reach the desired current accuracy. if no indication is given, then the gbr function is assumed to be enabled ( lgcr.gbrn bit set to ?1?). it is recommended to keep gbr circuitry enabled for open load at on diagnosis. the circuitry that controls gbr function can be deactivated with the following spi command sequence: ? swcr.swr = 1 (spi command: 11001100 b ) ? lgcr.gbrn = 0 (spi command: 1101aaaa b where ? aaaa ? b is the new value for lgcr.gbrn bits) ? (optional but recommended: swcr.swr = 0 (spi command: 11000100 b ) refer to chapter 9.7 for more details.
BTS54220-LBA diagnosis data sheet 49 rev. 2.0, 2014-05-26 8.5 electrical characteristics unless otherwise specified: v s = 7 v to 18 v, v dd = 3.8 v to 5.5 v, t j = -40 c to +150 c typical values: v s = 13.5 v, v dd = 4.3 v , t j = 25 c typical resistive loads connected to the outputs (unless otherwise specified): 9 m ? channels: r l = 2.2 ? 27 m ? channels: r l = 6.8 ? (33 ? when lgcr.ledn = ?1?) measurement setup used for k ilis (unless otherwise specified): channel 1, 4: when i l 1.3 a both channels are on at the same time with equal i l , channels 2, 3 have i l = 0 channel 2, 3: when i l 1.3 a both channels are on at the same time with equal i l , channels 1, 4 have i l = 0 when i l 2.0 a only the measured channel is on, all other channels have i l = 0 table 10 electrical characteristics diagnosis k ilis 9m ? ch. parameter symbol values unit note / test condition number min. typ. max. current sense ratio i l04 = 450 ma k ilis04 -67 % 4500 +142 % ? p_8.5.5 current sense ratio i l05 = 600 ma k ilis05 -56 % 4500 +56 % ? p_8.5.6 current sense ratio i l07 = 1.3 a k ilis07 -33 % 4500 +41 % lgcr.gbrn = 0 p_8.5.8 current sense ratio i l09 = 2.6 a k ilis09 -18 % 4500 +18 % lgcr.gbrn = 0 p_8.5.10 current sense ratio i l10 = 4 a k ilis10 -15 % 4500 +15 % ? p_8.5.11 current sense ratio i l11 = 7.5 a k ilis11 -11 % 4500 +11 % ? p_8.5.12 table 11 electrical characteristics diagnosis k ilis 27 m ? ch. parameter symbol values unit note / test condition number min. typ. max. current sense ratio signal in the nominal area, stable load current condition 27 m ? ch. current sense ratio i l03 = 300 ma k ilis03 -42 % 2000 +42 % ? p_8.5.28 current sense ratio i l05 = 600 ma k ilis05 -33 % 2000 +33 % ? p_8.5.30 current sense ratio i l07 = 1.3 a k ilis07 -21 % 2000 +21 % ? p_8.5.32 current sense ratio i l09 = 2.6 a k ilis09 -12 % 2000 +12 % ? p_8.5.34 current sense ratio i l10 = 4 a k ilis10 -11 % 2000 +11 % ? p_8.5.35
BTS54220-LBA diagnosis data sheet 50 rev. 2.0, 2014-05-26 current sense ratio signal in the nominal area, stable load current condition 27 m ? ch. in led mode current sense ratio i l00 = 20 ma k ilis00 -52 % 620 +52 % ? p_8.5.37 current sense ratio i l02 = 150 ma k ilis02 -33 % 570 +33 % ? p_8.5.39 current sense ratio i l03 = 300 ma k ilis03 -25 % 570 +25 % lgcr.gbrn = 0 p_8.5.40 current sense ratio i l05 = 600 ma k ilis05 -14 % 570 +14 % ? p_8.5.42 current sense ratio i l06 = 1 a k ilis06 -11 % 570 +11 % ? p_8.5.43 table 12 electrical characteristics diagnosis parameter symbol values unit note / test condition number min. typ. max. sense pin maximum voltage v is(az) 42 47 54 v i is = 5 ma p_8.5.75 current sense drift over current and temperature per device current sense drift over current and temperature per device 9 m ? ch. k ilis(t) -10 ? 10 % 1) k ilis11 versus k ilis09 p_8.5.76 current sense drift over current and temperature per device 27 m ? ch. k ilis(t) -8?8% 1) k ilis09 versus k ilis07 lgcr.ledn = 0 p_8.5.77 current sense drift over current and temperature per device 27 m ? ch. in led mode k ilis(t) -9.5 ? 9.5 % 1) k ilis05 versus k ilis03 lgcr.ledn = 1 p_8.5.78 table 11 electrical characteristics diagnosis k ilis 27 m ? ch. (cont?d) parameter symbol values unit note / test condition number min. typ. max.
BTS54220-LBA diagnosis data sheet 51 rev. 2.0, 2014-05-26 current sense drift of unaffected channel during inverse current of other channels one channel with i l(ic) = - i ln , all other channels with i ln dcr.mux <111, 110> and set to sense any of the channels not in inverse current condition current sense drift of unaffected channels during inverse current of one channel k ilis(ic) -20 ? 20 % 1) i l1 = 7.5 a i l2 = 2.6 a i l3 = 2.6 a i l4 = 7.5 a p_8.5.83 sense pin - currents maximum steady state current sense output current 9 m ? ch. i is(max) 4.5 ? 15 ma v is = 0 v v s 8v p_8.5.86 maximum steady state current sense output current 27 m ? ch. i is(max) 3.8 ? 15 ma v is = 0 v v s 8v p_8.5.87 current sense leakage / offset current i is(en) ??1 a 1) t j 85 c i l = 0 ma dcr.mux <111,110> b p_8.5.118 current sense leakage / offset current i is(en) ??3.2 a t j = 150 c i l = 0 ma dcr.mux <111,110> b p_8.5.90 open load detection threshold in on state 9 m ? ch. i l(ol) ??48.5ma i is(ol) = 4 a p_8.5.91 open load detection threshold in on state 27 m ? ch. i l(ol) ??21.5ma i is(ol) = 4 a lgcr.ledn = 0 p_8.5.93 open load detection threshold in on state 27 m ? ch. in led mode i l(ol) ??7.5ma i is(ol) = 4 a lgcr.ledn = 1 p_8.5.94 current sense leakage, while diagnosis disabled i is(dis) ?0.011 a i l2 = 2.6 a dcr.mux = 110 b p_8.5.98 sense pin - timings current sense settling time after channel activation 9 m ? ch. t sis(on) ??250 s v s = 13.5 v r is = 2.7 k ? p_8.5.99 current sense settling time after channel activation 27 m ? ch. t sis(on) ??250 s v s = 13.5 v r is = 2.7 k ? lgcr.ledn = 0 p_8.5.101 table 12 electrical characteristics diagnosis (cont?d) parameter symbol values unit note / test condition number min. typ. max.
BTS54220-LBA diagnosis data sheet 52 rev. 2.0, 2014-05-26 current sense settling time after channel activation 27 m ? ch. in led mode t sis(on) ??100 s v s = 13.5 v r is = 2.7 k ? lgcr.ledn = 1 p_8.5.102 current sense desettling time after channel deactivation t dis(off) ??25 s v s = 13.5 v r is = 2.7 k ? p_8.5.106 current sense settling time after change of load current 9 m ? ch. t sis(lc) ??25 s 1) i l = 4a to 2.6a v s = 13.5 v r is = 2.7 k ? p_8.5.107 current sense settling time after change of load current 27 m ? ch. t sis(lc) ??25 s 1) i l = 2.6 a to 1.3 a v s = 13.5 v r is = 2.7 k ? lgcr.ledn = 0 p_8.5.109 current sense settling time after change of load current 27 m ? ch. in led mode t sis(lc) ??25 s 1) i l = 1.3 a to 0.6 a v s = 13.5 v r is = 2.7 k ? lgcr.ledn = 1 p_8.5.110 current sense settling time after current sense activation t sis(en) ??25 s r is = 2.7 k ? i l2 = 2.6 a dcr.mux : 110 b 001 b p_8.5.114 current sense settling time after multiplexer channel change t sis(mux) ??25 s r is = 2.7 k ? i l2 = 2.6 a i l3 = 4 a dcr.mux : 001 b 010 b p_8.5.115 current sense deactivation time t dis(mux) ??25 s 1) r is = 2.7 k ? dcr.mux : 010 b 110 b p_8.5.116 switch bypass monitor switch bypass monitor threshold v ds(sb) 1.5 3.3 4.5 v off state p_8.5.117 1) not subject to production test, specified by design. table 12 electrical characteristics diagnosis (cont?d) parameter symbol values unit note / test condition number min. typ. max.
BTS54220-LBA serial peripheral interface (spi) data sheet 53 rev. 2.0, 2014-05-26 9 serial peripheral interface (spi) the serial peripheral interface (spi) is a full duplex sync hronous serial slave interface, which uses four lines: so, si, sclk and cs. data is transferred by the lines si a nd so at the rate given by sclk. the falling edge of cs indicates the beginning of an access. da ta is sampled in on line si at the falling edge of sclk and shifted out on line so at the rising edge of sclk. each access must be terminated by a rising edge of cs. a modulo 8 counter ensures that data is taken only when a multiple of 8 bit has been transferred. the interface provides daisy chain capability with 8 bit spi devices. figure 25 serial peripheral interface 9.1 spi signal description cs - chip select the system micro controller selects the BTS54220-LBA by means of the cs pin. whenever the pin is in ?low? state, data transfer can take place. when cs is in ?high? state, any signals at the sclk an d si pins are ignored and so is forced into a high impedance state. cs ?high? to ?low? transition ? the requested information is transferred into the shift register. ? so changes from high impedance state to ?high? or ?low? state depending on the signal level at pin si. figure 26 combinatorial logic for ter flag 6 5 4 3 2 1 lsb 6 5 4 3 2 1 cs msb so si cs sclk time spi _8bit.emf lsb msb spi _ ter.e m f si spi or ter 0 1 so cs scl k s so s si
BTS54220-LBA serial peripheral interface (spi) data sheet 54 rev. 2.0, 2014-05-26 cs ?low? to ?high? transition ? command decoding is only d one, when after the falling edge of cs exactly a multiple (1, 2, 3, ?) of eight sclk signals have been detected. in case of faul ty transmission, the transmission error flag ( ter ) is set and the command is ignored. ? data from shift register is transferred into the addressed register. sclk - serial clock this input pin clocks the in ternal shift register. the serial input (si) transfers da ta into the shift register on the falling edge of sclk while the serial output (s o) shifts diagnostic information out on the rising edge of the serial clock. it is essential that the sclk pin is in ?low? state when ever chip select cs makes any transition, otherwise the command may be not accepted. si - serial input serial input data bits are shift-in at this pin, the most significant bit first. si information is read on the falling edge of sclk. the input data consists of two parts, co ntrol bits followed by data bits. please refer to chapter 9.5 for further information. so serial output data is shifted out serially at this pi n, the most significant bit first. so is in high impedance state until the cs pin goes to ?low? state. new data will appear at the so pin followi ng the rising edge of sclk. please refer to chapter 9.5 for further information. 9.2 daisy chain capability the spi of BTS54220-LBA provides dai sy chain capability. in this configur ation several devices are activated by the same cs signal mcs. the si line of one device is connected with the so lin e of another device (see figure 27 ), in order to build a chain. the end of the chain is connected to the output and input of the master device, mo and mi respectively. the master dev ice provides the master clock mclk which is connected to the sclk line of each device in the chain. figure 27 daisy chain configuration in the spi block of each device, there is one shift register where each bit from si line is shifted in each sclk. the bit shifted out occurs at the so pin. after eight sclk cycl es, the data transfer for one device is finished. in single chip configuration, the cs line must turn ?high? to make the device ackn owledge the transferred data. in daisy chain configuration, the data shifted out at device 1 ha s been shifted in to device 2. when using three devices in daisy chain, three times 8 bits have to be shifted throug h the devices. after that, th e mcs line must turn ?high? (see figure 28 ). si device 1 spi sclk so cs si device 2 spi sclk so cs si device 3 spi sclk so cs mo mi mcs mclk spi_daisychain.emf
BTS54220-LBA serial peripheral interface (spi) data sheet 55 rev. 2.0, 2014-05-26 figure 28 data transfer in daisy chain configuration 9.3 timing diagrams figure 29 timing diagram spi access mi mo mcs mclk si device 1 si device 2 si device 3 so device 1 so device 2 so device 3 time spi _daisychain_2.emf cs sclk si t cs(lead) t cs(td) t cs(lag) t sc l k (h ) t sc l k ( l ) t sc l k( p ) t si ( s u) t si (h ) so t so( v ) t so(en) t so (d is ) spi _timings.emf v cs(h) v cs(l) v sc l k( h ) v sc l k( l ) v si( h ) v si( l ) v so( h ) v so( l )
BTS54220-LBA serial peripheral interface (spi) data sheet 56 rev. 2.0, 2014-05-26 9.4 electrical characteristics unless otherwise specified: v s = 7 v to 18 v, t j = -40 c to +150 c, v dd = 3.8v to 5.5v typical values: v s = 13.5 v, t j = 25 c, v dd = 4.3 v table 13 electrical characteristics serial peripheral interface (spi) parameter symbol values unit note / test condition number min. typ. max. input characteristics (cs, sclk, si) - l level of pin cs v cs(l) -0.3 ? 1.0 v v dd = 4.3 v p_9.4.1 sclk v sclk(l) -0.3 ? 1.0 v v dd = 4.3 v p_9.4.2 si v si(l) -0.3 ? 1.0 v v dd = 4.3 v p_9.4.3 input characteristics (cs, sclk, si) - h level of pin cs v cs(h) 2.6 ? v dd v v dd = 4.3 v p_9.4.4 sclk v sclk(h) 2.6 ? v dd v v dd = 4.3 v p_9.4.5 si v si(h) 2.6 ? v dd v v dd = 4.3 v p_9.4.6 l-input pull-up current at cs pin -i cs(l) 73075 a v dd = 4.3 v v cs = 1.0 v p_9.4.7 h-input pull-up current at cs pin -i cs(h) 32775 a v dd = 4.3 v v cs = 2.6 v p_9.4.8 l-input pull-down current at pin sclk i sclk(l) 32775 a v sclk = 1.0 v v dd = 4.3 v p_9.4.9 si i si(l) 32775 a v si = 1.0 v v dd = 4.3 v p_9.4.10 h-input pull-down current at pin sclk i sclk(h) 73075 a v sclk = 2.6 v v dd = 4.3 v p_9.4.11 si i si(h) 73075 a v si = 2.6 v v dd = 4.3 v p_9.4.12 output characteristics (so) l level output voltage v so(l) 0?0.5v i so = -0.5 ma p_9.4.13 h level output voltage v so(h) v dd - 0.5 v ? v dd v i so = 0.5 ma v dd = 4.3 v p_9.4.14 output tristate leakage current i so(off) -1 ? 1 a v cs = v dd v so = 0 v v so = v dd p_9.4.15 timings enable lead time (falling cs to rising sclk) t cs(lead) 200??ns? 1) p_9.4.16 enable lag time (falling sclk to rising cs) t cs(lag) 200??ns? 1) p_9.4.17 transfer delay time (rising cs to falling cs) t cs(td) 1?? s? 1) p_9.4.18
BTS54220-LBA serial peripheral interface (spi) data sheet 57 rev. 2.0, 2014-05-26 output enable time (falling cs to so valid) t so(en) ??1 s 1) c l = 50 pf p_9.4.19 output disable time (rising cs to so tristate) t so(dis) ??1 s 1) c l = 50 pf p_9.4.20 serial clock frequency f sclk 0?3mhz? 1) p_9.4.22 serial clock period t sclk(p) 333??ns? 1) p_9.4.24 serial clock ?high? time t sclk(h) 150??ns? 1) p_9.4.26 serial clock ?low? time t sclk(l) 150??ns? 1) p_9.4.28 data setup time (required time si to falling sclk) t si(su) 65??ns? 1) p_9.4.30 data hold time (falling sclk to si) t si(h) 65??ns? 1) p_9.4.32 output data valid time with capacitive load t so(v) ??166ns 1) c l = 50 pf p_9.4.34 1) not subject to production test, specified by design table 13 electrical characteristics serial peripheral interface (spi) (cont?d) parameter symbol values unit note / test condition number min. typ. max.
BTS54220-LBA serial peripheral interface (spi) data sheet 58 rev. 2.0, 2014-05-26 9.5 spi protocol the relationship between si and so content during spi communication is shown in figure 30 . si line represents the frame sent from the c and so line is the answer provided by BTS54220-LBA. the ?(previous response)? means that the frame sent back depends on the command frame sent from the c before. figure 30 relationship between si and so during spi communication the spi protocol provides the answer to a command frame only with the next transmission triggered by the c. although the biggest majority of commands and frames implemented in BTS54220-LBA can be decoded without the knowledge of what happened before, it is advisable to consider what the c sent in the previous transmission to decode BTS54220-LBA response frame completely. more in detail, the sequence of comma nds to ?read? and ?w rite? the content of a regi ster will look as follows: figure 31 register content sent back to c there are 3 special situations where the frame sent back to the c doesn't depend on the previous received frame: ? in case an error in transmission happened during the previous frame (for instance, the clock pulses were not multiple of 8), shown in figure 32 ? when BTS54220-LBA logic supply comes out of power-on reset condition, as shown in figure 33 ? when v s < v smon and dcr.mux 111 b , as shown in figure 34 figure 32 BTS54220-LBA response after an error in transmission si so frame a frame b (previous response) response to frame a frame c response to frame b spi_ si2 so.emf si so write register a read register a standard diagnostic register a content (new command ) spi_rwseq.emf (previous response) frame a (error in transmission ) spi_so_ter.emf si so (new command) standard diagnostic + ter (previous response )
BTS54220-LBA serial peripheral interface (spi) data sheet 59 rev. 2.0, 2014-05-26 figure 33 BTS54220-LBA response after coming out of power-on reset at v dd figure 34 BTS54220-LBA response in case of a negative battery voltage transient a summary of all possible spi commands is presented in table 14 , including the answer that BTS54220-LBA will send back at the next transmission. si so frame a frame b (so = ?z?) frame c response to frame b standard diagnosis + ter v dd(po) spi _so_ por.emf v dd si so spi_so_vsmon.emf v smon,max t v s v smon,min 0 vsmon x 1 t x 0 (response ) frame a frame b frame c frame d std . diag . + ter + vsmon std. diag. + ter + vsmon (response to frame c)
BTS54220-LBA serial peripheral interface (spi) data sheet 60 rev. 2.0, 2014-05-26 table 14 spi command summary requested operation frame sent to spoc+ (si pin) frame received from spoc+ (so pin) with the next command write out register 100xaaaa b where: ? xaaaa b ? = new out register content (? xx b ? = don't care) 0aaaaaaa b (standard diagnosis) read out register 00xx0000 b (? xx b ? = don't care) 10aaaaaa b (? aaaaaa b ? = out register content) write configuration register 11aabbbb b where: ? aa b ? = register address ? bbbb b ? = new register content 0aaaaaaa b (standard diagnosis) read configuration register 01aa0000 b where: ? aa b ? = register address 11aabbbb b where: ? aa b ? = register address ? bbbb b ? = register content read standard diagnosis 0xxx0001 b (? xxx b ? = don't care) 0aaaaaaa b (standard diagnosis) read errors diagnosis 0xxx0011 b (? xxx b ? = don't care) 00aaaaaa b (error diagnosis) read warnings diagnosis 0xxx0101 b (? xxx b ? = don't care) 00aaaaaa b (warning diagnosis)
BTS54220-LBA serial peripheral interface (spi) data sheet 61 rev. 2.0, 2014-05-26 9.6 spi diagnosis registers 9.6.1 standard diagnosis so76543210default 0 ter lhi stb vsmon err_mux 50 h field bits type description ter 6r transmission error 0 b previous transmission was successful (modulo 8 clocks received) 1 b (default) previous transmission failed or first transmission after reset lhi 5r limp home monitor 0 b (default) normal mode operation 1 b limp home mode stb 4r standby mode monitor 0 b normal mode operation 1 b (default) stand-by mode vsmon 3r v s monitor 0 b (default) v s always > v smon since last standard diagnosis readout 1 b v s < v smon at least once err_mux 2:0 r diagnosis of channel n in error 000 b (default) no channel latched off 001 b channel one latched off 010 b channel two latched off 011 b channel three latched off 100 b channel four latched off 101 b not used 110 b not used 111 b more than one channel latched off
BTS54220-LBA serial peripheral interface (spi) data sheet 62 rev. 2.0, 2014-05-26 9.6.2 errors diagnosis 9.6.3 warnings diagnosis so76543210default 0001 err_countern 10 h field bits type description err_countern n = 4 to 1 3:0 r diagnosis of channel n 0 b (default) no failure 1 b over temperature counter reached to n retry so76543210default 0010 errn 20 h field bits type description errn n = 4 to 1 3:0 r warning diagnosis of channel n 0 b (default) no failure 1 b over temperature counter > 0
BTS54220-LBA serial peripheral interface (spi) data sheet 63 rev. 2.0, 2014-05-26 9.7 spi configuration registers the following table provides an overview on the re gisters available and the available addressing space. 9.7.1 output config uration register 9.7.2 input status register 9.7.3 swap configuration register table 15 register overview register name register bank address swcr.swr bit content out 0 (na) 0 output configuration out 0 (na) 1 input status swcr 1 00 (na) swap configuration lgcr 1 01 0 led mode configuration lgcr 1 01 1 gate back regulation configuration hwcr 1 10 (na) hardware configuration dcr 1 11 (na) diagnostic configuration swcr.swr = 0 bit76543210 name w = 1 r = 0 rb543210default out w/r 0 0 x out.outn 80 h swcr.swr = 1 bit76543210 name w = 1 r = 0 rb543210default out r0 lhi 1 out.instn 90 h bit76543210default name w = 1 r = 0 rb addr 3210 swcr w/r 1 00 swcr.swr 100c4 h
BTS54220-LBA serial peripheral interface (spi) data sheet 64 rev. 2.0, 2014-05-26 9.7.4 led mode conf iguration register 9.7.5 gate back re gulation register 9.7.6 hardware configuration register swcr.swr = 0 name w = 1 r = 0 rb addr 3 2 1 0 default lgcr w/r 1 01 0 lgcr.ledn 0d0 h swcr.swr = 1 name w = 1 r = 0 rb addr 3 2 1 0 default lgcr w/r 1 01 lgcr.gbrn df h name w = 1 r = 0 rb addr 3 2 1 0 default hwcr r110 hwcr.rcr hwcr.col hwcr.stb 0e2 h w110 hwcr.rcr hwcr.col hwcr.rst hwcr.ctc -
BTS54220-LBA serial peripheral interface (spi) data sheet 65 rev. 2.0, 2014-05-26 9.7.7 diagnosis control register 9.7.8 configuration re gister bit overview name w = 1 r = 0 rb addr 3 2 1 0 default dcr r111 dcr.sbm dcr.mux f7 h w111 0 dcr.mux - field bits type description rb 6rw register bank 0 b (default) read / write to out register 1 b read / write to other registers out.outn n = 4 to 1 3:0 rw output control register of channel n 0 b (default) channel is off 1 b channel is on out.instn n = 4 to 1 3:0 r input status monitor channel n 0 b (default) input signal is ?low? 1 b input signal is ?high? lgcr.ledn n = 3 to 2 2:1 rw set led mode for channel n 0 b (default) channel n is in bulb mode 1 b channel n is in led mode lgcr.gbrn n = 4 to 1 3:0 rw gate back regulation for channel n 0 b gate back regulation for channel n is forced off 1 b (default) gate back regulation for channel n is active hwcr.ctc 0w clear thermal counter 0 b (default) thermal latches are untouched 1 b command: clear all thermal latches hwcr.rst 1w reset command 0 b (default) normal operation 1 b execute reset command hwcr.stb 1r standby mode 0 b device is awake 1 b (default) device is in standby mode hwcr.col 2rw input combinatorial logic configuration 0 b (default) input signal or-combined with according out register bit 1) 1 b input signal and-combined with according out register bit hwcr.rcr 3rw retry counter reset 0 b (default) retry counter is reset only for hwcr.ctc =1 (and v dd reset) 1 b retry counter is reset for every in-pin or out.outn ?high? to ?low? transition for n retry < n retry,max and also for hwcr.ctc =1 (and v dd reset)
BTS54220-LBA serial peripheral interface (spi) data sheet 66 rev. 2.0, 2014-05-26 swcr.swr 1rw switch register 0 b (default) out.outn and lgcr.ledn can be written and read 1 b out.instn can be read and lgcr.gbrn can be written and read dcr.sbm 3r switch bypass monitor 2) 0 b v ds < v ds(sb) 1 b v ds > v ds(sb) dcr.mux 2:0 rw set current sense multiplexer configuration in off-state 000 b is pin is high impedance 001 b is pin is high impedance 010 b is pin is high impedance 011 b is pin is high impedance 100 b is pin is high impedance 101 b is pin is high impedance 110 b is pin is high impedance 111 b stand-by mode (is pin is high impedance) set multiplexer config uration in on-state 000 b current sense of channel 1 is routed to is pin 001 b current sense of channel 2 is routed to is pin 010 b current sense of channel 3 is routed to is pin 011 b current sense of channel 4 is routed to is pin 100 b is pin is high impedance 101 b is pin is high impedance 110 b is pin is high impedance 111 b stand-by mode (is pin is high impedance)) 1) in limp home mode (lhi pin set to ?high?) the combinatorial logic is switched to or-mode. 2) the switch bypass monitor compares the threshold v ds(sb) with the voltage v ds across the power transistor of that channel which is selected by the current sense multiplexer ( dcr.mux ). field bits type description
BTS54220-LBA application description data sheet 67 rev. 2.0, 2014-05-26 10 application description the following figure describes a typical operating circui t. it shall not be considered as a warranty of a certain functionality, condition or quality of the device. the table 16 shows suggested component values and purposes. figure 35 application circuit example spi vs out4 out3 out2 out1 65w 27w 27w 65w is so sclk si cs gnd lhi wd- out r lhi vdd gnd vdd c vdd c e.g . xc2267 vss vcc v bat ad 5v r vdd spi r so r si r sclk r cs gpio in2 in3 in1 wd- out c vs1 c gnd in4 c adc z1 z2 c vs2 d gnd r in r in r in r in application _220noed.emf r rec r gn d c out r se n s e r 1 r adc
BTS54220-LBA application description data sheet 68 rev. 2.0, 2014-05-26 table 16 suggested component values reference value purpose r vdd 500 ? device logic protection (size 1206 recommended) r in 8 k ? protection of the c during ov ervoltage, reverse polarity and loss of ground r 1 4.7 k ? protection resistor for overvoltage, reverse polarity and loss of ground. value to be tuned with c specification r is 2.7 k ? sense resistor r adc 1 k ? c-adc voltage spikes filtering r cs 3.9 k ? protection of the c during ov ervoltage and reverse polarity r sclk 3.9 k ? protection of the c during ov ervoltage and reverse polarity r so 3.9 k ? protection of the c during ov ervoltage and reverse polarity r si 3.9 k ? protection of the c during ov ervoltage and reverse polarity r lhi 8 k ? protection of the c during ov ervoltage and reverse polarity c adc 1 nf c-adc voltage spikes filtering c vdd 100 nf logic supply vo ltage spikes filtering c vs1 68 nf battery voltage spikes filtering c vs2 100 nf battery voltage spikes filtering c out 10 nf for improved electrom agnetic compatibility (emc) c gnd 8.2 nf ground voltage spikes filtering (optional for improved robustness against battery voltage transients) r gnd 100 ? ground voltage spikes filtering (optional for improved robustness against battery voltage transients) r rec 1 k ? ground voltage recycling path (optional for providing a recycle path in case of loss of battery) z 1 7 v protection of c duri ng overvoltage. zener diode z 2 p6smb30 protection of device du ring overvoltage. zener diode d gnd bas70 protection of device during reverse polarity. schottky diode
BTS54220-LBA package outlines BTS54220-LBA data sheet 69 rev. 2.0, 2014-05-26 11 package outlin es BTS54220-LBA figure 36 tson-24-3 package drawing
BTS54220-LBA package outlines BTS54220-LBA data sheet 70 rev. 2.0, 2014-05-26 figure 37 tson-24 package pads and stencil green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). note: you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products .
edition 2014-05-26 published by infineon technologies ag 81726 munich, germany ? 2014 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. legal disclaimer for short-circuit capability infineon disclaims any warranties and lia bilities, whether expresse d nor implied, for any sh ort-circuit failures below the threshold limit. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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